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Code Activity
yosys/techlibs/xilinx
History
Eddie Hung 691686f92c Tidy up, fix undriven
2019-09-19 20:04:52 -07:00
..
tests Add pattern detection support for DSP48E1 model, check against vendor 2019-09-18 10:45:04 -07:00
.gitignore
abc_map.v Tidy up, fix undriven 2019-09-19 20:04:52 -07:00
abc_model.v Fix DSP48E1 timing by breaking P path if MREG or PREG 2019-09-19 18:59:28 -07:00
abc_unmap.v $__ABC_REG to have WIDTH parameter 2019-09-19 19:37:45 -07:00
abc_xc7.box Fix DSP48E1 timing by breaking P path if MREG or PREG 2019-09-19 18:59:28 -07:00
abc_xc7.lut
abc_xc7_nowide.lut
arith_map.v
brams_init.py
cells_map.v
cells_sim.v Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp 2019-09-19 15:47:41 -07:00
cells_xtra.py Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00
dsp_map.v D is 25 bits not 24 bits wide 2019-09-19 15:55:49 -07:00
lut_map.v
lutrams.txt
lutrams_map.v
Makefile.inc Merge remote-tracking branch 'origin/master' into xc7dsp 2019-09-18 12:23:22 -07:00
mux_map.v
synth_xilinx.cc Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp 2019-09-19 15:47:41 -07:00
xc6s_brams.txt
xc6s_brams_bb.v
xc6s_brams_map.v
xc6s_cells_xtra.v Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00
xc6s_ff_map.v synth_xilinx: Support init values on Spartan 6 flip-flops properly. 2019-09-07 16:30:43 +02:00
xc6v_cells_xtra.v Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00
xc7_brams.txt
xc7_brams_bb.v Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00
xc7_brams_map.v
xc7_cells_xtra.v Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00
xc7_ff_map.v synth_xilinx: Support init values on Spartan 6 flip-flops properly. 2019-09-07 16:30:43 +02:00
xcu_cells_xtra.v Use extractinv for synth_xilinx -ise 2019-09-19 04:02:48 +02:00