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25 lines
887 B
Text
25 lines
887 B
Text
read_verilog -icells <<EOT
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module top(input E, S, R, D, output [5:0] Q);
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$_DLATCH_PP0_ ff0 (.E(E), .R(R), .D(D), .Q(Q[0]));
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$_DLATCH_PN0_ ff1 (.E(E), .R(R), .D(D), .Q(Q[1]));
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$_DLATCH_PP1_ ff2 (.E(E), .R(R), .D(D), .Q(Q[2]));
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$_DLATCH_PN1_ ff3 (.E(E), .R(R), .D(D), .Q(Q[3]));
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$_DLATCHSR_PPP_ ff4 (.E(E), .S(S), .R(R), .D(D), .Q(Q[4]));
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$_DLATCHSR_PNP_ ff5 (.E(E), .S(S), .R(R), .D(D), .Q(Q[5]));
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endmodule
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EOT
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design -save orig
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logger -expect warning "Emulating async reset latch with a plain D latch" 4
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logger -expect warning "Emulating async set \+ reset latch with a plain D latch" 2
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equiv_opt -assert -multiclock dfflegalize -cell $_DLATCH_P_ x
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logger -check-expected
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design -load orig
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dfflegalize -cell $_DLATCH_P_ x
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select -assert-count 6 t:$_DLATCH_P_
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select -assert-count 0 t:$_DLATCHSR_???_
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select -assert-count 0 t:$_DLATCH_??0_
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select -assert-count 0 t:$_DLATCH_??1_
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