Eddie Hung a2ef93f03a abc -> abc9		2019-10-04 17:56:38 -07:00
..
tests
.gitignore
abc9_map.v	Fix merge issues	2019-10-04 17:21:14 -07:00
abc9_model.v	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	2019-10-04 16:58:55 -07:00
abc9_unmap.v	Fix merge issues	2019-10-04 17:21:14 -07:00
abc9_xc7.box	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	2019-10-04 16:58:55 -07:00
abc9_xc7.lut	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00
abc9_xc7_nowide.lut	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00
arith_map.v
brams_init.py
cells_map.v
cells_sim.v	Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff	2019-10-04 16:58:55 -07:00
cells_xtra.py	Remove DSP48E1 from *_cells_xtra.v	2019-10-04 17:26:42 -07:00
dsp_map.v	D is 25 bits not 24 bits wide	2019-09-19 15:55:49 -07:00
lut_map.v
lutrams.txt
lutrams_map.v
Makefile.inc	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00
mux_map.v
synth_xilinx.cc	abc -> abc9	2019-10-04 17:56:38 -07:00
xc6s_brams.txt
xc6s_brams_bb.v	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00
xc6s_brams_map.v
xc6s_cells_xtra.v	Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}	2019-09-30 12:52:43 +02:00
xc6s_ff_map.v	synth_xilinx: Support latches, remove used-up FF init values.	2019-09-30 12:52:43 +02:00
xc6v_cells_xtra.v	Remove DSP48E1 from *_cells_xtra.v	2019-10-04 17:26:42 -07:00
xc7_brams.txt
xc7_brams_bb.v	Rename abc_* names/attributes to more precisely be abc9_*	2019-10-04 11:04:10 -07:00
xc7_brams_map.v
xc7_cells_xtra.v	Remove DSP48E1 from *_cells_xtra.v	2019-10-04 17:26:42 -07:00
xc7_ff_map.v	synth_xilinx: Support latches, remove used-up FF init values.	2019-09-30 12:52:43 +02:00
xcu_cells_xtra.v	Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py}	2019-09-30 12:52:43 +02:00