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29 lines
613 B
Text
29 lines
613 B
Text
# loop involving the asynchronous reset on a memory port
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design -reset
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read -vlog2k <<EOF
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module top(input wire clk, input wire [3:0] addr, output reg [3:0] data);
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reg [3:0] mem [15:0];
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reg [5:0] i;
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initial begin
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for (i = 0; i < 16; i = i + 1)
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mem[i] = i * 371;
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end
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wire arst = !data[0];
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always @(posedge arst, posedge clk) begin
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if (arst)
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data <= 4'hx;
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else
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data <= mem[addr];
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end
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endmodule
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EOF
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hierarchy -top top
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proc
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opt -keepdc
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memory_dff
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opt_clean
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logger -nowarn "found logic loop in module pingpong:"
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logger -expect error "Found [0-9]+ problems in 'check -assert'" 1
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check -assert
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