Miodrag Milanović d0a41d4f58 Merge pull request #5442 from rocallahan/verific-bus-ports ... Set `port_id` for Verific `PortBus` wires		2025-11-03 10:04:07 +01:00
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aiger
alumacc
arch	gowin: fix test	2025-09-23 20:03:50 +02:00
asicworld
bind
blif
bram
bugpoint
cxxrtl
errors
fmt
fsm
functional
hana
liberty	libcache: support liberty filename globbing	2025-09-24 11:41:51 +02:00
lut
memfile
memlib
memories
opt	Merge pull request #3991 from adrianparvino/alumacc-sign	2025-10-08 13:02:10 +02:00
opt_share
peepopt
proc
pyosys	pyosys: fix ref-only classes, implicit conversions	2025-10-03 11:54:44 +03:00
realmath
rpc
rtlil	Don't stop parsing sigspec after a {} group.	2025-10-14 21:18:58 +00:00
sat
select
share
sim	Revert sim's cycle_width default back to 10, but keep -width option	2025-10-20 14:40:05 +02:00
simple
simple_abc9
smv
sva
svinterfaces
svtypes
techmap	dfflibmap: fix next_state inversion propagation for DFF flops by inverting reset value polarity	2025-10-28 13:56:28 +01:00
tools
unit
various	plugins: add search path	2025-10-15 14:13:25 +03:00
verific	Set port_id for Verific PortBus wires	2025-10-23 20:51:53 +00:00
verilog
vloghtb
xprop
.gitignore
gen-tests-makefile.sh