mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
12 lines
156 B
Verilog
12 lines
156 B
Verilog
module m;
|
|
parameter PARAM = 0;
|
|
endmodule
|
|
|
|
(* foo="bar" *)
|
|
(* val=32'hffffffff *)
|
|
module top;
|
|
(* dont_touch *)
|
|
wire w;
|
|
|
|
m #(.PARAM(-3)) inst();
|
|
endmodule
|