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14 lines
206 B
Text
14 lines
206 B
Text
read_verilog <<EOT
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module top(input clk, inout [7:0] x);
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reg [3:0] ctr;
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always @(posedge clk) ctr <= ctr + 1'b1;
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assign x[7:4] = ctr;
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endmodule
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EOT
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proc
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tribuf
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deminout
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select -assert-count 1 i:x o:x %i
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