mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 03:32:29 +00:00
12 lines
207 B
Verilog
12 lines
207 B
Verilog
module dynslice (
|
|
input clk ,
|
|
input [9:0] ctrl ,
|
|
input [15:0] din ,
|
|
input [3:0] sel ,
|
|
output reg [127:0] dout
|
|
);
|
|
always @(posedge clk)
|
|
begin
|
|
dout[ctrl*sel+:16] <= din ;
|
|
end
|
|
endmodule
|