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yosys/passes/proc
2025-11-19 11:34:05 +01:00
..
Makefile.inc Add proc_rom pass. 2022-05-13 00:37:14 +02:00
proc.cc Add proc_rom pass. 2022-05-13 00:37:14 +02:00
proc_arst.cc rtlil: add source tracking to CaseRule actions 2025-11-19 11:34:05 +01:00
proc_clean.cc rtlil: replace SigSig actions with new type SyncAction 2025-11-19 11:34:05 +01:00
proc_dff.cc proc_dff: add wire src attributes to dff cells 2025-11-19 11:34:05 +01:00
proc_dlatch.cc rtlil: replace SigSig actions with new type SyncAction 2025-11-19 11:34:05 +01:00
proc_init.cc rtlil: replace SigSig actions with new type SyncAction 2025-11-19 11:34:05 +01:00
proc_memwr.cc Update passes/proc to avoid bits() 2025-09-16 03:17:23 +00:00
proc_mux.cc proc_mux: optimize source map locality for index density 2025-11-19 11:34:05 +01:00
proc_prune.cc rtlil: replace SigSig actions with new type SyncAction 2025-11-19 11:34:05 +01:00
proc_rmdead.cc Proc: Use selections consistently 2025-05-31 12:04:42 +12:00
proc_rom.cc rtlil: add source tracking to CaseRule actions 2025-11-19 11:34:05 +01:00