Eddie Hung d406f2ffd7 Merge pull request #1569 from YosysHQ/eddie/fix_1531 ... verilog: preserve size of $genval$-s in for loops		2019-12-19 12:21:33 -05:00
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.gitignore
abc9.v
abc9.ys
async.sh
async.v
attrib05_port_conn.v
attrib05_port_conn.ys
attrib07_func_call.v
attrib07_func_call.ys
bug1462.ys
bug1480.ys
bug1496.ys
bug1531.ys
chparam.sh
constmsk_test.v
constmsk_test.ys
constmsk_testmap.v
elab_sys_tasks.sv
elab_sys_tasks.ys
equiv_opt_multiclock.ys
gzip_verilog.v.gz
gzip_verilog.ys
hierarchy.sh
hierarchy_defer.ys
mem2reg.ys
muxcover.ys
muxpack.v
muxpack.ys
peepopt.ys
pmgen_reduce.ys
pmux2shiftx.v
pmux2shiftx.ys
reg_wire_error.sv
reg_wire_error.ys
run-test.sh
scratchpad.ys
script.ys
shregmap.v
shregmap.ys
signext.ys
specify.v
specify.ys
submod_extract.ys
svalways.sh
wreduce.ys
write_gzip.ys