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tests
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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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2019-08-12 12:06:45 -07:00 |
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.gitignore
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Initialization support for all iCE40 bram modes
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2015-04-26 08:39:31 +02:00 |
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abc_hx.box
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Rename boxes too
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2019-08-29 07:03:32 -07:00 |
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abc_hx.lut
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Fix rename
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2019-04-18 09:04:34 -07:00 |
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abc_lp.box
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Rename boxes too
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2019-08-29 07:03:32 -07:00 |
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abc_lp.lut
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Rename to abc_*.{box,lut}
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2019-04-18 09:02:58 -07:00 |
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abc_u.box
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Rename boxes too
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2019-08-29 07:03:32 -07:00 |
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abc_u.lut
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Rename to abc_*.{box,lut}
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2019-04-18 09:02:58 -07:00 |
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arith_map.v
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Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
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2019-08-12 12:06:45 -07:00 |
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brams.txt
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Added read-enable to memory model
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2015-09-25 12:23:11 +02:00 |
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brams_init.py
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Switched to Python 3
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2015-08-22 09:59:33 +02:00 |
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brams_map.v
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ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
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2019-02-28 16:23:40 -08:00 |
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cells_map.v
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Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER
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2019-08-12 12:19:25 -07:00 |
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cells_sim.v
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Comment out SB_MAC16 arrival time for now, need to handle all its modes
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2019-08-28 19:09:29 -07:00 |
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dsp_map.v
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Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing
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2019-08-08 12:56:05 -07:00 |
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ice40_braminit.cc
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substr() -> compare()
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2019-08-07 12:20:08 -07:00 |
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ice40_ffinit.cc
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Consistent use of 'override' for virtual methods in derived classes.
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2018-07-20 23:51:06 -07:00 |
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ice40_ffssr.cc
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ice40: Honor the "dont_touch" attribute in FFSSR pass
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2018-12-08 22:46:28 +01:00 |
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ice40_opt.cc
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Do not overwrite LUT param
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2019-08-28 18:46:53 -07:00 |
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latches_map.v
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Added synth_ice40 support for latches via logic loops
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2016-05-06 23:02:37 +02:00 |
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Makefile.inc
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Merge branch 'master' into xc7dsp
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2019-08-30 13:57:15 +01:00 |
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synth_ice40.cc
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Only wreduce on t:$add
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2019-09-25 17:22:04 -07:00 |
