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Code Activity
yosys/tests/arch
History
Marcelina Kościelnicka 347dd01c2f xilinx: Fix srl regression. 
Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and
$_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the
point where xilinx_srl is called for non-abc9.  Fix this by running
ff_map.v first, resulting in FDRE cells, which are handled correctly.
2020-07-12 23:41:27 +02:00
..
anlogic Simplify breaking tests/arch/*/fsm.ys tests 2020-03-20 11:25:17 -07:00
common ecp5: add support for both 1364.1 and LSE RAM/ROM attributes. 2020-02-06 16:52:51 +00:00
ecp5 tests: tidy up testcase 2020-06-03 08:41:55 -07:00
efinix Simplify breaking tests/arch/*/fsm.ys tests 2020-03-20 11:25:17 -07:00
gowin gowin: Use dfflegalize. 2020-07-06 12:27:46 +02:00
ice40 allow range for mux test 2020-06-01 13:48:19 +02:00
intel_alm intel_alm: direct M10K instantiation 2020-07-05 23:28:59 +02:00
xilinx xilinx: Fix srl regression. 2020-07-12 23:41:27 +02:00
run-test.sh tests: extend tests/arch/run-tests.sh for defines 2020-03-05 08:08:32 -08:00