Eddie Hung c20adc5263 Add test		2019-06-20 16:07:22 -07:00
..
.gitignore
aes_kexp128.v
always01.v
always02.v
always03.v
arraycells.v
arrays01.v
arrays02.sv	Add proper test for SV-style arrays	2019-06-20 12:06:07 +02:00
attrib01_module.v
attrib02_port_decl.v
attrib03_parameter.v
attrib04_net_var.v
attrib05_port_conn.v.DISABLED
attrib06_operator_suffix.v
attrib07_func_call.v.DISABLED
attrib08_mod_inst.v
attrib09_case.v
carryadd.v
constmuldivmod.v
constpower.v
defvalue.sv	Add defvalue test, minor autotest fixes for .sv files	2019-06-19 12:12:08 +02:00
dff_different_styles.v
dff_init.v
fiedler-cooley.v
forgen01.v
forgen02.v
forloops.v
fsm.v
generate.v	Add test	2019-06-20 16:07:22 -07:00
graphtest.v
hierarchy.v
hierdefparam.v
i2c_master_tests.v
implicit_ports.v	Rename implicit_ports.sv test to implicit_ports.v	2019-06-07 13:12:25 +02:00
localparam_attr.v
loops.v
macros.v
mem2reg.v
mem_arst.v
memory.v
multiplier.v
muxtree.v
omsp_dbg_uart.v
operators.v
param_attr.v
paramods.v
partsel.v
peepopt.v
process.v
realexpr.v
repwhile.v
retime.v
rotate.v
run-test.sh	SystemVerilog support for implicit named port connections	2019-06-06 18:07:49 +02:00
scopes.v
signedexpr.v
sincos.v
specify.v
subbytes.v
task_func.v
undef_eqx_nex.v
usb_phy_tests.v
values.v
vloghammer.v
wandwor.v
wreduce.v
xfirrtl