Eddie Hung 2f4e0a5388 Merge remote-tracking branch 'origin/master' into xaig_dff		2019-08-19 10:07:27 -07:00
..
tests	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"	2019-08-12 12:06:45 -07:00
.gitignore
abc_hx.box	$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark	2019-07-15 12:03:51 -07:00
abc_hx.lut	Fix rename	2019-04-18 09:04:34 -07:00
abc_lp.box	$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark	2019-07-15 12:03:51 -07:00
abc_lp.lut	Rename to abc_*.{box,lut}	2019-04-18 09:02:58 -07:00
abc_u.box	$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark	2019-07-15 12:03:51 -07:00
abc_u.lut	Rename to abc_*.{box,lut}	2019-04-18 09:02:58 -07:00
arith_map.v	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"	2019-08-12 12:06:45 -07:00
brams.txt
brams_init.py
brams_map.v	ice40: use 2 bits for READ/WRITE MODE for SB_RAM map	2019-02-28 16:23:40 -08:00
cells_map.v	Fix $lut pin ordering inside $__ICE40_CARRY_WRAPPER	2019-08-12 12:19:25 -07:00
cells_sim.v	Update abc_* attr in ecp5 and ice40	2019-08-16 15:56:57 -07:00
ice40_braminit.cc	substr() -> compare()	2019-08-07 12:20:08 -07:00
ice40_ffinit.cc
ice40_ffssr.cc	ice40: Honor the "dont_touch" attribute in FFSSR pass	2018-12-08 22:46:28 +01:00
ice40_opt.cc	RTLIL::S{0,1} -> State::S{0,1}	2019-08-07 11:12:38 -07:00
latches_map.v
Makefile.inc	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"	2019-08-12 12:06:45 -07:00
synth_ice40.cc	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"	2019-08-12 12:06:45 -07:00