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2e37e62e6b
By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
24 lines
559 B
Verilog
24 lines
559 B
Verilog
module __MISTRAL_VCC(output Q);
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MISTRAL_ALUT2 #(.LUT(4'b1111)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
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endmodule
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module __MISTRAL_GND(output Q);
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MISTRAL_ALUT2 #(.LUT(4'b0000)) _TECHMAP_REPLACE_ (.A(1'b1), .B(1'b1), .Q(Q));
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endmodule
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module MISTRAL_FF(input D, CLK, ACn, ALD, AD, EN, output reg Q);
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parameter INIT = 1'b0;
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localparam [1023:0] INIT_STR = (INIT !== 1'b1) ? "low" : "high";
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dffeas #(.power_up(INIT_STR), .is_wysiwyg("true")) _TECHMAP_REPLACE_ (.d(D), .clk(CLK), .clrn(ACn), .aload(ALD), .asdata(AD), .ena(EN), .q(Q));
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endmodule
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