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yosys/techlibs/intel_alm/Makefile.inc
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00

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1.4 KiB
Makefile

OBJS += techlibs/intel_alm/synth_intel_alm.o
# Techmap
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/alm_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/alm_sim.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/arith_alm_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_map.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/dff_sim.v))
# RAM
bramtypes := m10k m20k
$(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_$(bramtype).txt)))
$(foreach bramtype, $(bramtypes), $(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/bram_$(bramtype)_map.v)))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab.txt))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/lutram_mlab_map.v))
families := cyclonev cyclone10gx
# Miscellaneous
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/megafunction_bb.v))
$(eval $(call add_share_file,share/intel_alm/common,techlibs/intel_alm/common/quartus_rename.v))
$(foreach family, $(families), $(eval $(call add_share_file,share/intel_alm/$(family),techlibs/intel_alm/$(family)/quartus_rename.v)))