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66 lines
2.3 KiB
Plaintext
66 lines
2.3 KiB
Plaintext
read_verilog <<EOT
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module foo(
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input [7:0] A,
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input [7:0] B,
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input [7:0] C,
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input [7:0] D,
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output reg [7:0] X,
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output reg [7:0] Y);
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assign X = A * B;
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assign Y = C * D;
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endmodule
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EOT
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synth_quicklogic -run :map_dsp
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# this is just taken from map_dsp step
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wreduce t:$mul
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ql_dsp_macc
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techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18
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chtype -set $mul t:$__soft_mul
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techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9
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techmap -map +/quicklogic/qlf_k6n10f/dspv1_map.v -D USE_DSP_CFG_PARAMS=0
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read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim.v
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read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim_extra.v
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select -assert-count 2 t:dsp_t1_10x9x32_cfg_ports
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select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports_fracturable
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equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v -map +/quicklogic/qlf_k6n10f/dspv1_sim_extra.v ql_dsp_simd
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design -load postopt
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select -assert-count 0 t:dsp_t1_10x9x32_cfg_ports
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select -assert-count 1 t:dsp_t1_20x18x64_cfg_ports_fracturable
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design -reset
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read_verilog <<EOT
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module foo(
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input [7:0] A,
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input [7:0] B,
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input [7:0] C,
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input [7:0] D,
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input [7:0] E,
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output reg [7:0] X,
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output reg [7:0] Y);
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assign X = A * B;
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assign Y = C * (D + E); // <-- look here
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endmodule
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EOT
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synth_quicklogic -run :map_dsp
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wreduce t:$mul
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ql_dsp_macc
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techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18
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chtype -set $mul t:$__soft_mul
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techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9
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techmap -map +/quicklogic/qlf_k6n10f/dspv1_map.v -D USE_DSP_CFG_PARAMS=0
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read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim.v
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read_verilog -lib +/quicklogic/qlf_k6n10f/dspv1_sim_extra.v
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select -assert-count 2 t:dsp_t1_10x9x32_cfg_ports
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select -assert-count 0 t:dsp_t1_20x18x64_cfg_ports_fracturable
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equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/dspv1_sim.v -map +/quicklogic/qlf_k6n10f/dspv1_sim_extra.v ql_dsp_simd
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design -load postopt
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select -assert-count 0 t:dsp_t1_10x9x32_cfg_ports
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select -assert-count 1 t:dsp_t1_20x18x64_cfg_ports_fracturable
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