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.gitignore
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quicklogic: Initial blockram tests
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2023-12-04 15:52:03 +01:00 |
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add_sub.ys
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quicklogic: Add basic k6n10f tests
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2023-12-04 15:52:03 +01:00 |
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adffs.ys
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quicklogic: Add basic k6n10f tests
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2023-12-04 15:52:03 +01:00 |
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counter.ys
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quicklogic: Add basic k6n10f tests
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2023-12-04 15:52:03 +01:00 |
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dffs.ys
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quicklogic: Fix dffs.ys test
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2023-12-04 15:52:03 +01:00 |
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div.ys
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quicklogic: Relax the LUT number test
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2024-10-07 15:27:03 +02:00 |
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dspv1_full.ys
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quicklogic: rename dspv1 full synth_quicklogic test for clarity
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2025-03-10 14:29:03 +01:00 |
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dspv1_simd.ys
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quicklogic: add fracturable full-block dspv1 to keep vendor simulation model unchanged
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2025-03-10 17:12:31 +01:00 |
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dspv2_simd.ys
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quicklogic: remove irrelevant comments in dspv2 test
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2025-03-10 14:29:03 +01:00 |
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fsm.ys
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quicklogic: Add basic k6n10f tests
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2023-12-04 15:52:03 +01:00 |
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latches.ys
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quicklogic: Add basic k6n10f tests
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2023-12-04 15:52:03 +01:00 |
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logic.ys
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quicklogic: Add basic k6n10f tests
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2023-12-04 15:52:03 +01:00 |
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mem_gen.py
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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mem_tb.v
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qlf_tests: minor adjustment
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2023-12-04 15:52:03 +01:00 |
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meminit.v
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quicklogic: Test TDP36K inference with initial data
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2023-12-04 15:52:03 +01:00 |
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meminit.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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mux.ys
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quicklogic: Add basic k6n10f tests
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2023-12-04 15:52:03 +01:00 |
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run-test.sh
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test: restore verific handling, nicer naming
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2024-12-13 10:24:47 +01:00 |
