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81 lines
2.1 KiB
Verilog
81 lines
2.1 KiB
Verilog
// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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`timescale 1ps/1ps
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`default_nettype none
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// dsp_t1_20x18x64_cfg_ports but with input wire f_mode_i
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// This is a yosys-specific extension beyond the vendor-provided model
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module dsp_t1_20x18x64_cfg_ports_fracturable (
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input wire [19:0] a_i,
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input wire [17:0] b_i,
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input wire [ 5:0] acc_fir_i,
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output wire [37:0] z_o,
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output wire [17:0] dly_b_o,
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(* clkbuf_sink *)
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input wire clock_i,
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input wire reset_i,
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input wire [ 2:0] feedback_i,
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input wire load_acc_i,
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input wire unsigned_a_i,
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input wire unsigned_b_i,
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input wire [ 2:0] output_select_i,
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input wire saturate_enable_i,
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input wire [ 5:0] shift_right_i,
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input wire round_i,
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input wire subtract_i,
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input wire register_inputs_i,
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input wire f_mode_i
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);
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parameter [19:0] COEFF_0 = 20'd0;
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parameter [19:0] COEFF_1 = 20'd0;
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parameter [19:0] COEFF_2 = 20'd0;
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parameter [19:0] COEFF_3 = 20'd0;
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QL_DSP2 #(
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.MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
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) dsp (
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.a(a_i),
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.b(b_i),
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.z(z_o),
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.dly_b(dly_b_o),
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.f_mode(f_mode_i), // 20x18x64 DSP
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.acc_fir(acc_fir_i),
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.feedback(feedback_i),
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.load_acc(load_acc_i),
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.unsigned_a(unsigned_a_i),
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.unsigned_b(unsigned_b_i),
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.clk(clock_i),
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.reset(reset_i),
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.saturate_enable(saturate_enable_i),
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.output_select(output_select_i),
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.round(round_i),
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.shift_right(shift_right_i),
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.subtract(subtract_i),
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.register_inputs(register_inputs_i)
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);
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endmodule
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