mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 09:55:20 +00:00
2b9c75f8e3
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
41 lines
959 B
Verilog
41 lines
959 B
Verilog
module sub_mod(input i_in, output o_out);
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assign o_out = i_in;
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endmodule
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module test(i_clk, i_reg, o_reg, o_wire);
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input i_clk;
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input i_reg;
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output o_reg;
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output o_wire;
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// Enable this to see how it doesn't fail on yosys although it should
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//reg o_wire;
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// Enable this instead of the above to see how logic can be mapped to a wire
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logic o_wire;
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// Enable this to see how it doesn't fail on yosys although it should
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//reg i_reg;
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// Disable this to see how it doesn't fail on yosys although it should
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reg o_reg;
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logic l_reg;
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// Enable this to tst if logic-turne-reg will catch assignments even if done before it turned into a reg
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//assign l_reg = !o_reg;
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initial o_reg = 1'b0;
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always @(posedge i_clk)
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begin
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o_reg <= !o_reg;
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l_reg <= !o_reg;
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end
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assign o_wire = !o_reg;
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// Uncomment this to see how a logic already turned intoa reg can be freely assigned on yosys
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//assign l_reg = !o_reg;
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sub_mod sm_inst (
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.i_in(1'b1),
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.o_out(o_reg)
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);
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endmodule
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