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yosys/passes
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Matt Johnston 2a3804139f opt_mem_merge: Combine memories for byte enable. 
The RAMs inferred by GHDL are split into separate instances
for byte enables. This pass recombines memories that have the same
input address (and matching characteristics) allowing a single
BRAM to be used with byte enables.

Work in progress, needs more checks for memory compatibility
Briefly tested to work for microwatt
2022-01-14 14:40:04 +08:00
..
cmds bugpoint: avoid infinite loop between -connections and -wires. 2021-12-15 08:17:02 +00:00
equiv Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
fsm Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
hierarchy verilog: use derived module info to elaborate cell connections 2021-10-25 18:25:50 -07:00
memory opt_mem_merge: Combine memories for byte enable. 2022-01-14 14:40:04 +08:00
opt opt_mem_merge: Combine memories for byte enable. 2022-01-14 14:40:04 +08:00
pmgen Make it work on all 2021-11-05 10:51:58 +01:00
proc proc_dff: Emit $aldff. 2021-10-27 14:14:24 +02:00
sat FfData: some refactoring. 2021-10-07 04:24:06 +02:00
techmap sta: very crude static timing analysis pass 2021-11-25 17:20:27 +01:00
tests Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00