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yosys/techlibs/ice40
2019-09-26 09:57:11 -07:00
..
tests
.gitignore
abc_hx.box Rename boxes too 2019-08-29 07:03:32 -07:00
abc_hx.lut
abc_lp.box Rename boxes too 2019-08-29 07:03:32 -07:00
abc_lp.lut
abc_u.box Rename boxes too 2019-08-29 07:03:32 -07:00
abc_u.lut
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v
cells_sim.v Comment out SB_MAC16 arrival time for now, need to handle all its modes 2019-08-28 19:09:29 -07:00
dsp_map.v
ice40_braminit.cc
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc
latches_map.v Added synth_ice40 support for latches via logic loops 2016-05-06 23:02:37 +02:00
Makefile.inc Merge branch 'master' into xc7dsp 2019-08-30 13:57:15 +01:00
synth_ice40.cc Stop trying to be too smart by prematurely optimising 2019-09-26 09:57:11 -07:00