3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 13:18:56 +00:00
yosys/tests
Jeff Wang 249876b614 support using previously declared types/localparams/params in package
(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
..
aiger tests/aiger: Add missing .gitignore 2020-02-15 19:52:21 +01:00
arch Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor 2020-04-01 14:17:01 -07:00
asicworld
bram
errors
fsm
hana
liberty
lut
memfile Added 'set -e' into tests/memfile/run-test.sh 2020-02-06 10:45:40 -03:00
memories
opt Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor 2020-04-01 14:17:01 -07:00
opt_share
proc proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
realmath
rpc rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors 2020-03-06 15:29:01 +01:00
sat Merge pull request #1638 from YosysHQ/eddie/fix1631 2020-02-05 19:31:18 +01:00
select Do not warn on empty selection with prefixed arg_memb. 2020-03-23 17:50:11 +00:00
share
simple Add dynamic slicing Verilog testcase 2020-03-31 11:51:31 -07:00
simple_abc9 Update simple_abc9 tests 2020-02-27 10:17:29 -08:00
smv
sva
svinterfaces
svtypes support using previously declared types/localparams/params in package 2020-04-07 00:38:15 -04:00
techmap Merge pull request #1648 from YosysHQ/eddie/cmp2lcu 2020-04-03 16:28:25 -07:00
tools
unit
various Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
vloghtb