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Code
Activity
242c5f01de
yosys
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passes
History
Clifford Wolf
cf25dc9ce7
Copy attributes to _TECHMAP_REPLACE_ cells
2017-02-16 12:28:42 +01:00
..
cmds
Added "check -initdrv"
2017-01-04 18:12:41 +01:00
equiv
Add $ff and $_FF_ support to equiv_simple
2017-01-30 10:50:38 +01:00
fsm
Be more conservative with merging large cells into FSMs
2017-01-26 09:19:28 +01:00
hierarchy
Do not fix port widths on any blackbox instances
2017-02-13 17:07:38 +01:00
memory
Typo fix.
2016-09-08 10:57:16 +03:00
opt
Fixed some "used uninitialized" warnings in opt_expr
2017-02-11 10:50:48 +01:00
proc
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
sat
Bugfix in "miter -assert" handling of assumptions
2016-10-17 14:56:58 +02:00
techmap
Copy attributes to _TECHMAP_REPLACE_ cells
2017-02-16 12:28:42 +01:00
tests
Cosmetic fix in test_autotb.cc
2016-09-19 20:43:43 +02:00