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13 lines
265 B
Text
13 lines
265 B
Text
verific -sv <<EOT
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module simple (
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input [3:0] I2,
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input [3:0] I1,
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output [3:0] result
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);
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assign result = I2 & I1;
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endmodule
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EOT
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verific -import simple
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write_verilog verilog_port_bus_order.out
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!grep -qF 'simple(I2, I1, result)' verilog_port_bus_order.out
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