Emil J. Tywoniak 3e45f9729e fix $specrule port naming		2026-04-13 22:34:46 +02:00
..
choices	Merge pull request #4789 from YosysHQ/emil/sklansky-adder	2024-12-03 11:33:13 +01:00
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py	cellhelp.py: Cells can have tags	2024-10-15 07:35:41 +13:00
cmp2lcu.v
cmp2lut.v
cmp2softlogic.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py
Makefile.inc	sdc_expand, opensta: start	2025-11-19 15:20:50 +01:00
mul2dsp.v
opensta.cc	opensta, sdc_expand: mark as experimental	2025-11-19 15:31:17 +01:00
opensta.h	opensta: refactor default command	2025-11-19 15:20:50 +01:00
pmux2mux.v
prep.cc	Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.	2026-01-23 01:14:35 +00:00
sdc_expand.cc	opensta, sdc_expand: mark as experimental	2025-11-19 15:31:17 +01:00
simcells.v	simcells: $dffsr and derivatives undefine S&R in logic tables	2026-03-19 19:27:30 +01:00
simlib.v	fix $specrule port naming	2026-04-13 22:34:46 +02:00
smtmap.v
synth.cc	Rename csa_tree to arith_tree.	2026-04-13 12:48:05 +02:00
techmap.v	techmap: map $alu to $fa instead of relying on extract_fa	2025-09-23 17:05:12 +02:00