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https://github.com/YosysHQ/yosys
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42 lines
905 B
Text
42 lines
905 B
Text
pattern muxadd
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//
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// Transforms add->mux into mux->add:
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// y = s ? (a + b) : a ===> y = a + (s ? b : 0)
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//
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state <SigSpec> add_y add_a add_b
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match add
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select add->type == $add
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endmatch
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code add_y add_a add_b
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add_y = port(add, \Y);
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add_a = port(add, \A);
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add_b = port(add, \B);
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branch;
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std::swap(add_a, add_b);
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endcode
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match mux
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select mux->type == $mux
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index <SigSpec> port(mux, \A) === SigSpec({Const(State::S0, GetSize(add_y)-GetSize(add_a)), add_a})
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index <SigSpec> port(mux, \B) === add_y
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endmatch
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code
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SigSpec mux_y = port(mux, \Y);
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SigSpec mid = module->addWire(NEW_ID, GetSize(add_b));
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mux->setPort(\A, Const(State::S0, GetSize(add_b)));
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mux->setPort(\B, add_b);
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mux->setPort(\Y, mid);
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add->setPort(\B, mid);
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add->setPort(\Y, mux_y);
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log("muxadd pattern in %s: mux=%s, add=%s\n", log_id(module), log_id(mux), log_id(add));
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mux->fixup_parameters();
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accept;
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endcode
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