Zachary Snow 1d5f3fe506 verlog: allow shadowing module ports within generate blocks ... This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.		2021-02-07 11:48:39 -05:00
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.gitignore	Add "make coverage"	2018-08-27 14:22:21 +02:00
const2ast.cc	Replacing log_error for log_file_error due consistency	2020-03-31 12:01:29 -06:00
Makefile.inc	Treat all bison warnings as errors in verilog front-end	2020-07-15 11:57:31 +02:00
preproc.cc	verilog: strip leading and trailing spaces in macro args	2021-01-28 11:26:35 -05:00
preproc.h	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
verilog_frontend.cc	Fix SYNTHESIS always being defined in Verilog frontend	2020-12-01 01:37:19 +00:00
verilog_frontend.h	frontend: cleanup to use more ID::*, more dict<> instead of map<>	2020-05-04 10:48:37 -07:00
verilog_lexer.l	Merge pull request #2179 from splhack/static-cast	2020-07-01 16:40:20 +02:00
verilog_parser.y	verlog: allow shadowing module ports within generate blocks	2021-02-07 11:48:39 -05:00