Zachary Snow 1d5f3fe506 verlog: allow shadowing module ports within generate blocks ... This is a somewhat obscure edge case I encountered while working on test cases for earlier changes. Declarations in generate blocks should not be checked against the list of ports. This change also adds a check forbidding declarations within generate blocks being tagged as inputs or outputs.		2021-02-07 11:48:39 -05:00
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aiger	Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().	2020-06-19 15:48:58 +00:00
ast	genrtlil: fix signed port connection codegen failures	2021-02-05 19:51:30 -05:00
blif	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
json	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
liberty	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
rpc	Fix argument handling in connect_rpc	2020-10-19 13:40:57 +02:00
rtlil	rtlil: remove dotted identifiers.	2020-11-25 16:47:20 +00:00
verific	Require latest Verific build	2021-01-30 09:23:46 +01:00
verilog	verlog: allow shadowing module ports within generate blocks	2021-02-07 11:48:39 -05:00