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Code Activity
yosys/backends
History
whitequark 1d5b6ac253 cxxrtl: add an unsupported knob for manipulating clock trees. 
This is quite possibly the worst way to implement this, but it does
work for a subset of well-behaved designs, and can be used to measure
how much performance is lost simulating the inactive edge of a clock.

It should be replaced with a clock tree analyzer generating safe
code once it is clear how should such a thing look like.
2020-04-22 01:15:27 +00:00
..
aiger xaiger: add check for $__ABC9_DELAY model 2020-04-13 19:11:23 -07:00
blif kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
btor kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
cxxrtl cxxrtl: add an unsupported knob for manipulating clock trees. 2020-04-22 01:15:27 +00:00
edif kernel: use more ID::* 2020-04-02 07:14:08 -07:00
firrtl ast, rpc: record original name of $paramod\* as \hdlname attribute. 2020-04-18 03:47:28 +00:00
ilang Clean up pseudo-private member usage in backends/ilang/ilang_backend.cc. 2020-04-01 03:08:39 +00:00
intersynth Clean up pseudo-private member usage in backends/intersynth/intersynth.cc. 2020-04-01 06:32:09 +00:00
json json: Update format documentation. 2020-04-15 16:12:14 +02:00
protobuf Add aiger and protobuf backends binary support 2019-09-28 09:51:48 +02:00
simplec kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
smt2 Merge pull request #1830 from boqwxp/qbfsat 2020-04-15 17:33:50 +02:00
smv kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
spice kernel: use more ID::* 2020-04-02 07:14:08 -07:00
table Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
verilog write_verilog: fix precondition check. 2020-04-14 12:12:50 +00:00