mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-05 09:04:08 +00:00
4 lines
83 B
Verilog
4 lines
83 B
Verilog
module sub #(parameter d=1) (input in, output out);
|
|
assign out = in;
|
|
endmodule
|