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13 lines
183 B
Plaintext
13 lines
183 B
Plaintext
read_verilog <<EOT
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module top();
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wire array[0:0];
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wire out;
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sub #(.d(1)) inst(
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.in(array[0]),
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.out(out)
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);
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endmodule
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EOT
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hierarchy -top top -libdir .
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