Marcelina Kościelnicka 56e7791760 verilog backend: Emit a wire for ports as well. ... Fixes #3177.		2022-01-31 01:08:41 +01:00
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aiger
blif
btor	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
cxxrtl	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
edif
firrtl	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
intersynth
json
protobuf
rtlil	rtlil: Dump empty connections when whole module is selected.	2021-12-12 01:22:06 +01:00
simplec
smt2	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
smv	Add $bmux and $demux cells.	2022-01-28 23:34:41 +01:00
spice
table
verilog	verilog backend: Emit a wire for ports as well.	2022-01-31 01:08:41 +01:00