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18d1ba7f1f
`mem_gen.py` based on quicklogic tests. Remove BUFG from `lutram.ys`. Extra `sync_ram_sp` models in `arch/common/blockram.v`. Add analogdevices to main makefile tests. Not all the other tests are passing, but that's fine for now.
113 lines
3 KiB
Text
113 lines
3 KiB
Text
design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r -chparam A_WIDTH 5
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proc
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memory -nomap
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equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 8 t:FFRE
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select -assert-count 8 t:RAMS32X1
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select -assert-none t:FFRE t:RAMS32X1 %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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dump
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select -assert-count 8 t:FFRE
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select -assert-count 8 t:RAMS64X1
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select -assert-none t:FFRE t:RAMS64X1 %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w3r
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proc
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memory -nomap
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equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w3r
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select -assert-count 24 t:FFRE
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select -assert-count 16 t:RAMD32X1
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select -assert-none t:FFRE t:RAMD32X1 %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w3r -chparam A_WIDTH 6
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proc
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memory -nomap
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equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w3r
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select -assert-count 24 t:FFRE
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select -assert-count 16 t:RAMD64X1
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select -assert-none t:FFRE t:RAMD64X1 %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r -chparam A_WIDTH 5 -chparam D_WIDTH 6
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proc
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memory -nomap
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equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 6 t:FFRE
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select -assert-count 6 t:RAMS32X1
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select -assert-none t:FFRE t:RAMS32X1 %% t:* %D
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design -reset
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read_verilog ../common/lutram.v
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hierarchy -top lutram_1w1r -chparam A_WIDTH 6 -chparam D_WIDTH 6
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proc
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memory -nomap
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equiv_opt -run :prove -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad
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memory
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opt -full
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
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design -load postopt
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cd lutram_1w1r
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select -assert-count 6 t:FFRE
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select -assert-count 6 t:RAMS64X1
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select -assert-none t:FFRE t:RAMS64X1 %% t:* %D
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