mirror of
https://github.com/YosysHQ/yosys
synced 2025-10-31 11:42:30 +00:00
56 lines
1.1 KiB
Text
56 lines
1.1 KiB
Text
read_verilog <<EOF
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module top();
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wire \a[0] ;
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wire \0b ;
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wire c;
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wire d_;
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wire d$;
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wire \$e ;
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wire \wire ;
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wire add = c + d$;
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endmodule
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EOF
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dump
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# Replace brackets with _
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select -assert-count 1 w:a[0]
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# Prefix first character numeric with _
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select -assert-count 1 w:\0b
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# Do nothing to simple identifiers
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select -assert-count 1 w:c
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select -assert-count 1 w:d_
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# Replace dollars with _
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# and resolve conflict with existing d_
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select -assert-count 1 w:d$
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# Public but starts with dollar is legal
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select -assert-count 1 w:$e
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# Colliding with keyword
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select -assert-count 1 w:wire
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# Don't touch internal names
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select -assert-count 1 w:$add$<<EOF:*$1_Y
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rename -unescape
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select -assert-count 1 w:a_0_
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select -assert-count 1 w:_0b
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select -assert-count 1 w:c
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select -assert-count 1 w:d_
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select -assert-count 1 w:d__1
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select -assert-count 1 w:_e
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select -assert-count 1 w:wire_
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select -assert-count 1 w:$add$<<EOF:*$1_Y
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# Ports are updated during rename
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design -reset
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read_verilog << EOT
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module top(output \$e );
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submod \a$ (\$e );
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endmodule
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module submod(output \a[0] );
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assign \a[0] = 0;
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endmodule
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EOT
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rename -unescape
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check
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