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yosys/frontends/verilog
garytwong 834a7294b7
verilog: fix string literal regular expression (#5187)
* verilog: fix string literal regular expression.

A backslash was improperly quoted, causing string literal matching
to fail when the final token before a closing quote was an escaped
backslash.

* verilog: add regression test for string literal regex bug.

Test for bug triggered by escaped backslash immediately before
closing quote (introduced in ca7d94af and fixed by 40aa7eaf).
2025-06-19 12:41:18 -04:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
Makefile.inc Treat all bison warnings as errors in verilog front-end 2020-07-15 11:57:31 +02:00
preproc.cc set default_nettype to wire for resetall 2022-08-10 13:28:19 +02:00
preproc.h verilog: save and restore overwritten macro arguments 2021-07-28 21:52:16 -04:00
verilog_frontend.cc read_verilog_file_list: change short help message to start with lower case 2025-04-08 13:20:16 +02:00
verilog_frontend.h verilog: Squash a memory leak. 2021-06-14 17:07:41 +02:00
verilog_lexer.l verilog: fix string literal regular expression (#5187) 2025-06-19 12:41:18 -04:00
verilog_parser.y Merge pull request #5152 from garytwong/unique-if 2025-06-13 09:56:53 +12:00