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Include mask/map for abc inputs (and switch to `anyconst` instead of `anyseq`). Add false divide check for mantissa. Covers aren't currently being tested by anything (and have to be removed for `sat`), but I've been using it locally with SBY to confirm that the different edge cases are able to be verified (e.g. when verifying HardFloat against symfpu while using the masked inputs to reduce solver time).
45 lines
855 B
Bash
Executable file
45 lines
855 B
Bash
Executable file
#!/usr/bin/env bash
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set -eu
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source ../gen-tests-makefile.sh
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rm -f *_edges.*
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prove_rm() {
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op=$1
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rm=$2
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defs=$3
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ys_file=${op}_${rm}_edges.ys
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echo "symfpu -op $op -rm $rm" > $ys_file
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if [[ $rm != "DYN" ]] then
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echo "sat -prove-asserts -verify" >> $ys_file
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fi
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echo """\
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chformal -remove
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opt
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read_verilog -sv -formal $defs -D${rm} edges.sv
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chformal -remove -cover
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chformal -lower
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prep -top edges -flatten
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sat -set-assumes -prove-asserts -verify
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""" >> $ys_file
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}
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prove_op() {
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op=$1
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defs=$2
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rms="RNE RNA RTP RTN RTZ DYN"
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for rm in $rms; do
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prove_rm $op $rm "$defs"
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done
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}
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prove_op sqrt "-DSQRT"
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prove_op add "-DADD -DADDSUB -DADDS"
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prove_op sub "-DSUB -DADDSUB -DADDS"
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prove_op mul "-DMUL -DMULS"
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prove_op div "-DDIV"
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prove_op muladd "-DMULADD -DMULS -DADDS"
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generate_mk --yosys-scripts
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