Miodrag Milanovic 3e9449cb0b make note that it is for latch mode		2019-09-18 17:48:16 +02:00
..
anlogic_eqn.cc	Fix formatting for msys2 mingw build using GetSize	2019-08-01 17:27:34 +02:00
anlogic_fixcarry.cc	Proper arith for Anlogic and use standard pass	2019-08-12 20:21:36 +02:00
arith_map.v	Fix missing newline at end of file	2019-08-22 18:09:37 +02:00
cells_map.v
cells_sim.v	make note that it is for latch mode	2019-09-18 17:48:16 +02:00
dram_init_16x4.vh
drams.txt
drams_map.v
eagle_bb.v
Makefile.inc	Proper arith for Anlogic and use standard pass	2019-08-12 20:21:36 +02:00
synth_anlogic.cc	Proper arith for Anlogic and use standard pass	2019-08-12 20:21:36 +02:00