Emil J. Tywoniak 8db06bb819 mul2dsp: declare $__mul and $__soft_mul so their ports have directions		2026-07-22 01:28:24 +02:00
..
achronix
analogdevices
anlogic	WIP migration to twine	2026-07-20 12:27:18 +02:00
common	mul2dsp: declare $__mul and $__soft_mul so their ports have directions	2026-07-22 01:28:24 +02:00
coolrunner2	coolrunner2: twines	2026-07-20 15:01:30 +02:00
easic
efinix	WIP migration to twine	2026-07-20 12:27:18 +02:00
fabulous
gatemate	WIP migration to twine	2026-07-20 12:27:18 +02:00
gowin	gowin: replace positional arguments in cells_sim.v with named	2026-07-17 23:33:02 +02:00
greenpak4	WIP migration to twine	2026-07-20 12:27:18 +02:00
ice40	ice40_opt: retire the wrapper's ports before reinterpreting it as $lut	2026-07-22 01:26:33 +02:00
intel	Revert "intel: register bram celltypes"	2026-07-17 23:38:01 +02:00
intel_alm	Revert "intel: register bram celltypes"	2026-07-17 23:38:01 +02:00
lattice	twines phase-3 build fix: post-fork main files broken by twine migration	2026-07-20 15:01:30 +02:00
microchip	WIP migration to twine	2026-07-20 12:27:18 +02:00
nanoxplore	techlibs: fix twines	2026-07-20 13:57:10 +02:00
quicklogic	techlibs: fix twines	2026-07-20 13:57:10 +02:00
sf2
xilinx	WIP migration to twine	2026-07-20 12:27:18 +02:00
CMakeLists.txt
fix_mod.py