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yosys/tests/liberty_verilog/busdef2.lib.v.ok
2024-10-05 01:34:12 -10:00

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(* blackbox = 1 *)
(* leakage_power_unit = "1pW" *)
module not_cell(A, Y);
input [7:0] A;
wire [7:0] A;
output Y;
wire Y;
endmodule