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14 lines
349 B
Text
14 lines
349 B
Text
# Check that opt_reduce doesn't produce zero width $reduce_or/$reduce_and,
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read_verilog <<EOT
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module reduce_const(output wire o, output wire a);
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wire [3:0] zero = 4'b0000;
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wire [3:0] ones = 4'b1111;
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assign o = |zero;
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assign a = &ones;
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endmodule
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EOT
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equiv_opt -assert opt_reduce
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design -load postopt
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select -assert-none r:A_WIDTH=0
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