Krystine Sherwin 1248af1e02 Tests: Prefer single quotes for regex ... Replaces double quotes on problematic regex strings (mostly ones that have escape sequences that are easier to preserve in single quotes). Necessitates also changing single quotes to `.`, i.e match any. For some (mostly ones that only have a single escaped character, or were using `\.` to match a literal fullstop) keep the double quotes and fix the regex instead.		2025-10-06 14:22:33 +13:00
..
.gitignore	Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.	2025-07-22 10:38:38 +00:00
abc9_dff.ys	Tests: Prefer single quotes for regex	2025-10-06 14:22:33 +13:00
add_sub.ys	xilinx: Initial support for LUT4 devices.	2020-02-07 09:03:22 +01:00
adffs.ys	Make test without iopads	2019-12-28 16:22:24 +01:00
asym_ram_sdp.ys	Asymmetric port ram tests with Xilinx	2023-02-21 05:23:14 +13:00
asym_ram_sdp_read_wider.v	Asymmetric port ram tests with Xilinx	2023-02-21 05:23:14 +13:00
asym_ram_sdp_write_wider.v	Asymmetric port ram tests with Xilinx	2023-02-21 05:23:14 +13:00
attributes_test.ys	Tests: Use setattr -setstr	2025-10-06 11:38:55 +13:00
blockram.ys	Tests: Use setattr -setstr	2025-10-06 11:38:55 +13:00
bug1460.ys	Make test without iopads	2019-12-28 16:22:24 +01:00
bug1462.ys	xilinx_dsp: another typo; move xilinx specific test	2020-01-17 17:07:03 -08:00
bug1480.ys	Cleanup tests	2020-02-27 10:17:29 -08:00
bug1598.ys	Add #1598 testcase	2019-12-27 16:44:57 -08:00
bug1605.ys	Added a test case	2020-01-01 16:24:30 +01:00
bug3670.v	ABC9: Cell Port Bug Patch (#3670)	2023-04-22 16:24:36 -07:00
bug3670.ys	ABC9: Cell Port Bug Patch (#3670)	2023-04-22 16:24:36 -07:00
counter.ys	Fix tests	2020-01-10 14:48:01 +01:00
dffs.ys	abc9_ops: -reintegrate to use derived_type for box_ports	2020-02-05 14:46:48 -08:00
dsp_abc9.ys	tests/arch/xilinx: Fix for warnings on boxes	2025-04-08 16:58:59 +12:00
dsp_cascade.ys	Fix new tests	2019-12-28 16:43:19 +01:00
dsp_fastfir.ys	Make test without iopads	2019-12-28 16:22:24 +01:00
dsp_simd.ys	Moved all tests in arch sub directory	2019-10-18 11:06:12 +02:00
fsm.ys	FfData: some refactoring.	2021-10-07 04:24:06 +02:00
latches.ys	opt_expr: Remove -clkinv option, make it the default.	2020-07-31 00:08:15 +02:00
logic.ys	Make test without iopads	2019-12-28 16:22:24 +01:00
lutram.ys	xilinx: Use memory_libmap pass.	2022-05-18 17:32:56 +02:00
macc.sh	xilinx_dsp: Initial DSP48A/DSP48A1 support.	2019-12-22 20:51:14 +01:00
macc.v	tests: xilinx macc test to have initval, shorten BMC depth for runtime	2020-05-25 10:09:05 -07:00
macc.ys	tests: xilinx macc test to have initval, shorten BMC depth for runtime	2020-05-25 10:09:05 -07:00
macc_tb.v	Moved all tests in arch sub directory	2019-10-18 11:06:12 +02:00
mul.ys	Fix new tests	2019-12-28 16:43:19 +01:00
mul_unsigned.v	Moved all tests in arch sub directory	2019-10-18 11:06:12 +02:00
mul_unsigned.ys	Fix new tests	2019-12-28 16:43:19 +01:00
mux.ys	xilinx_dffopt: Don't crash on missing IS_*_INVERTED.	2021-01-27 00:32:00 +01:00
mux_lut4.ys	Update tests	2023-06-09 14:41:45 +02:00
nosrl.ys	xilinx: Fix srl regression.	2020-07-12 23:41:27 +02:00
opt_lut_ins.ys	Remove references to ilang	2024-11-05 12:36:31 +13:00
pmgen_xilinx_srl.ys	satgen: Add support for dffe, sdff, sdffe, sdffce cells.	2020-07-24 03:19:21 +02:00
priority_memory.v	URAM mapping : Add test for 2048 x 144b	2025-05-10 14:53:56 +02:00
priority_memory.ys	URAM mapping : Add test for 2048 x 144b	2025-05-10 14:53:56 +02:00
run-test.sh	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
shifter.ys	Make test without iopads	2019-12-28 16:22:24 +01:00
tribuf.sh	Fix the tests we just broke	2021-12-10 00:22:37 +01:00
tribuf.ys	Addressed review comments	2019-12-21 20:23:23 +01:00
xilinx_dffopt.ys	Fix tests for check in equiv_opt	2022-10-07 16:04:51 +02:00
xilinx_dffopt_blacklist.txt	xilinx: Add xilinx_dffopt pass (#1557)	2019-12-18 13:43:43 +01:00
xilinx_dsp.ys	tests: read +/xilinx/cell_sim.v before xilinx_dsp test	2020-04-22 17:50:30 -07:00
xilinx_srl.v	tests: fix some test warnings	2020-05-25 10:07:58 -07:00
xilinx_srl.ys	Moved all tests in arch sub directory	2019-10-18 11:06:12 +02:00