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Code Activity
yosys/tests/verilog
History
Zachary Snow 220cb1f7bb verilog: error on macro invocations with missing argument lists 
This would previously complain about an undefined internal macro if the
unapplied macro had not already been used. If it had, it would
incorrectly use the arguments from the previous invocation.
2021-02-19 09:18:41 -05:00
..
.gitignore Update .gitignore 2020-10-01 15:53:14 +01:00
atom_type_signedness.ys Add missing is_signed to type_atom 2021-02-11 15:05:38 +01:00
block_labels.ys Add check of begin/end labels for genblock 2021-02-04 17:16:30 +01:00
bug656.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
bug656.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
bug2037.ys test: add attribute-before-stmt test from @nakengelhardt 2020-05-25 07:36:53 -07:00
bug2042-sv.ys tests: fix some test warnings 2020-05-25 10:07:58 -07:00
bug2042.ys tests: update/extend task argument tests 2020-05-13 10:11:45 -07:00
bug2493.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
const_arst.ys add tests 2020-09-28 18:16:08 +02:00
const_sr.ys add tests 2020-09-28 18:16:08 +02:00
genblk_case.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
genblk_case.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
genblk_port_decl.ys verlog: allow shadowing module ports within generate blocks 2021-02-07 11:48:39 -05:00
hidden_decl.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
macro_unapplied.ys verilog: error on macro invocations with missing argument lists 2021-02-19 09:18:41 -05:00
macro_unapplied_newline.ys verilog: error on macro invocations with missing argument lists 2021-02-19 09:18:41 -05:00
run-test.sh tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
task_attr.ys tests: attributes before task enable 2020-05-14 16:09:41 -07:00
unnamed_block.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
unnamed_genblk.sv verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
unnamed_genblk.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
upto.ys techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00
wire_and_var.sv sv: fix support wire and var data type modifiers 2021-01-20 09:16:21 -07:00
wire_and_var.ys sv: fix support wire and var data type modifiers 2021-01-20 09:16:21 -07:00