Krystine Sherwin afd5bbc7fa fstdata.cc: Fix last step ... Includes test file for sanity checking simulation steps.		2025-05-12 13:18:19 +12:00
..
tb
.gitignore
adff.v
adffe.v
adlatch.v
aldff.v
aldffe.v
assume_x_first_step.ys	Assume x values for missing signal data in FST	2024-10-02 12:08:48 +02:00
dff.v
dffe.v
dffsr.v
dlatch.v
dlatchsr.v
run-test.sh	test: restore verific handling, nicer naming	2024-12-13 10:24:47 +01:00
sdff.v
sdffce.v
sdffe.v
sim_adff.ys
sim_adffe.ys
sim_adlatch.ys
sim_aldff.ys
sim_aldffe.ys
sim_cycles.ys	fstdata.cc: Fix last step	2025-05-12 13:18:19 +12:00
sim_dff.ys
sim_dffe.ys
sim_dffsr.ys
sim_dlatch.ys
sim_dlatchsr.ys
sim_sdff.ys
sim_sdffce.ys
sim_sdffe.ys
simple_assign.v	Assume x values for missing signal data in FST	2024-10-02 12:08:48 +02:00
simple_assign.vcd	Assume x values for missing signal data in FST	2024-10-02 12:08:48 +02:00
var_reference_with_whitespace.vcd	Fix: handle VCD variable references with and without whitespace	2024-10-01 11:51:20 +02:00
var_reference_without_whitespace.vcd	Fix: handle VCD variable references with and without whitespace	2024-10-01 11:51:20 +02:00
vcd_var_reference_whitespace.ys	Fix: handle VCD variable references with and without whitespace	2024-10-01 11:51:20 +02:00
vector_assign.il	Fix: handle VCD variable references with and without whitespace	2024-10-01 11:51:20 +02:00