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.gitignore
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write_verilog: don't assign to a reg.
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2024-04-03 13:06:45 +02:00 |
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absurd_width.ys
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verilog: impose limit on maximum expression width
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2021-03-04 15:20:52 -05:00 |
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absurd_width_const.ys
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verilog: impose limit on maximum expression width
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2021-03-04 15:20:52 -05:00 |
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always_comb_latch_1.ys
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sv: auto add nosync to certain always_comb local vars
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2022-01-07 22:53:22 -07:00 |
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always_comb_latch_2.ys
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sv: auto add nosync to certain always_comb local vars
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2022-01-07 22:53:22 -07:00 |
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always_comb_latch_3.ys
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sv: auto add nosync to certain always_comb local vars
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2022-01-07 22:53:22 -07:00 |
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always_comb_latch_4.ys
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sv: auto add nosync to certain always_comb local vars
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2022-01-07 22:53:22 -07:00 |
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always_comb_nolatch_1.ys
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sv: auto add nosync to certain always_comb local vars
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2022-01-07 22:53:22 -07:00 |
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always_comb_nolatch_2.ys
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sv: auto add nosync to certain always_comb local vars
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2022-01-07 22:53:22 -07:00 |
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always_comb_nolatch_3.ys
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sv: auto add nosync to certain always_comb local vars
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2022-01-07 22:53:22 -07:00 |
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always_comb_nolatch_4.ys
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sv: auto add nosync to certain always_comb local vars
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2022-01-07 22:53:22 -07:00 |
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always_comb_nolatch_5.ys
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sv: fix always_comb auto nosync for nested and function blocks
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2022-04-05 14:43:48 -06:00 |
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always_comb_nolatch_6.ys
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sv: fix always_comb auto nosync for nested and function blocks
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2022-04-05 14:43:48 -06:00 |
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asgn_expr.sv
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fix width of post-increment/decrement expressions
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2023-09-18 23:46:06 -04:00 |
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asgn_expr.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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asgn_expr_not_proc_1.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_proc_2.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_proc_3.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_proc_4.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_proc_5.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_sv_1.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_sv_2.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_sv_3.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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asgn_expr_not_sv_4.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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assign_to_reg.ys
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Remove references to ilang
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2024-11-05 12:36:31 +13:00 |
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atom_type_signedness.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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block_end_label_only.ys
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sv: fix up end label checking
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2021-06-16 21:48:05 -04:00 |
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block_end_label_wrong.ys
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sv: fix up end label checking
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2021-06-16 21:48:05 -04:00 |
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block_labels.ys
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Standard compliance for tests/verilog/block_labels.ys
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2023-05-21 16:38:14 -04:00 |
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bug656.v
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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bug656.ys
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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bug2037.ys
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test: add attribute-before-stmt test from @nakengelhardt
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2020-05-25 07:36:53 -07:00 |
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bug2042-sv.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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bug2042.ys
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tests: update/extend task argument tests
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2020-05-13 10:11:45 -07:00 |
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bug2493.ys
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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conflict_assert.ys
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genrtlil: improve name conflict error messaging
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2021-02-26 18:08:23 -05:00 |
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conflict_cell_memory.ys
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genrtlil: improve name conflict error messaging
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2021-02-26 18:08:23 -05:00 |
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conflict_interface_port.ys
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genrtlil: improve name conflict error messaging
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2021-02-26 18:08:23 -05:00 |
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conflict_memory_wire.ys
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genrtlil: improve name conflict error messaging
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2021-02-26 18:08:23 -05:00 |
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conflict_pwire.ys
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genrtlil: improve name conflict error messaging
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2021-02-26 18:08:23 -05:00 |
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conflict_wire_memory.ys
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genrtlil: improve name conflict error messaging
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2021-02-26 18:08:23 -05:00 |
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const_arst.ys
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add tests
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2020-09-28 18:16:08 +02:00 |
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const_sr.ys
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add tests
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2020-09-28 18:16:08 +02:00 |
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delay_mintypmax.ys
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Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566)
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2021-02-24 15:48:15 -05:00 |
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delay_risefall.ys
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Extend "delay" expressions to handle pair and triplet, i.e. rise, fall and turn-off (#2566)
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2021-02-24 15:48:15 -05:00 |
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delay_time_scale.ys
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verilog: support for time scale delay values
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2022-02-14 15:58:31 +01:00 |
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doubleslash.ys
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fixup verilog doubleslash test
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2022-01-03 08:17:46 -07:00 |
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dynamic_range_lhs.sh
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Include x bits in test of lhs dynamic part-select
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2024-01-10 20:28:36 +01:00 |
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dynamic_range_lhs.v
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Include x bits in test of lhs dynamic part-select
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2024-01-10 20:28:36 +01:00 |
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for_decl_no_init.ys
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sv: support declaration in procedural for initialization
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2021-08-30 15:19:21 -06:00 |
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for_decl_no_sv.ys
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sv: support declaration in procedural for initialization
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2021-08-30 15:19:21 -06:00 |
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for_decl_shadow.sv
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sv: support declaration in procedural for initialization
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2021-08-30 15:19:21 -06:00 |
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for_decl_shadow.ys
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sv: support declaration in procedural for initialization
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2021-08-30 15:19:21 -06:00 |
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func_arg_mismatch_1.ys
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verilog: fix sizing of constant args for tasks/functions
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2021-02-21 15:44:43 -05:00 |
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func_arg_mismatch_2.ys
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verilog: fix sizing of constant args for tasks/functions
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2021-02-21 15:44:43 -05:00 |
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func_arg_mismatch_3.ys
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verilog: fix sizing of constant args for tasks/functions
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2021-02-21 15:44:43 -05:00 |
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func_arg_mismatch_4.ys
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verilog: fix sizing of constant args for tasks/functions
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2021-02-21 15:44:43 -05:00 |
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func_tern_hint.sv
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verilog: fix width/sign detection for functions
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2022-05-30 16:45:39 -04:00 |
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func_tern_hint.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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func_typename_ret.sv
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sv: allow typenames as function return types
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2021-03-19 12:08:43 -04:00 |
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func_typename_ret.ys
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sv: allow typenames as function return types
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2021-03-19 12:08:43 -04:00 |
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func_upto.sv
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verilog: fix const func eval with upto variables
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2022-02-11 21:01:51 +01:00 |
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func_upto.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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gen_block_end_label_only.ys
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sv: fix up end label checking
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2021-06-16 21:48:05 -04:00 |
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gen_block_end_label_wrong.ys
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sv: fix up end label checking
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2021-06-16 21:48:05 -04:00 |
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genblk_case.v
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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genblk_case.ys
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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genblk_port_decl.ys
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verlog: allow shadowing module ports within generate blocks
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2021-02-07 11:48:39 -05:00 |
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genfor_decl_no_init.ys
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sv: support declaration in generate for initialization
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2021-08-31 12:34:55 -06:00 |
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genfor_decl_no_sv.ys
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sv: support declaration in generate for initialization
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2021-08-31 12:34:55 -06:00 |
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genvar_loop_decl_1.sv
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sv: support declaration in generate for initialization
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2021-08-31 12:34:55 -06:00 |
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genvar_loop_decl_1.ys
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sv: support declaration in generate for initialization
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2021-08-31 12:34:55 -06:00 |
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genvar_loop_decl_2.sv
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sv: support declaration in generate for initialization
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2021-08-31 12:34:55 -06:00 |
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genvar_loop_decl_2.ys
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sv: support declaration in generate for initialization
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2021-08-31 12:34:55 -06:00 |
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genvar_loop_decl_3.sv
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sv: support declaration in generate for initialization
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2021-08-31 12:34:55 -06:00 |
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genvar_loop_decl_3.ys
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sv: support declaration in generate for initialization
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2021-08-31 12:34:55 -06:00 |
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global_parameter.ys
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verilog: disallow overriding global parameters
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2021-03-11 12:36:51 -05:00 |
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hidden_decl.ys
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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ifdef_nest.ys
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preproc: test coverage for #2712
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2021-03-30 12:23:18 -04:00 |
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ifdef_unterminated.ys
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preproc: test coverage for #2712
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2021-03-30 12:23:18 -04:00 |
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include_self.v
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verilog: fix handling of nested ifdef directives
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2021-03-01 12:28:33 -05:00 |
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include_self.ys
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verilog: fix handling of nested ifdef directives
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2021-03-01 12:28:33 -05:00 |
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int_types.sv
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sv: extended support for integer types
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2021-02-28 16:31:56 -05:00 |
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int_types.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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localparam_no_default_1.ys
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sv: support for parameters without default values
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2021-03-02 10:43:53 -05:00 |
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localparam_no_default_2.ys
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sv: support for parameters without default values
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2021-03-02 10:43:53 -05:00 |
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macro_arg_tromp.sv
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verilog: save and restore overwritten macro arguments
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2021-07-28 21:52:16 -04:00 |
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macro_arg_tromp.ys
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verilog: save and restore overwritten macro arguments
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2021-07-28 21:52:16 -04:00 |
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macro_unapplied.ys
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verilog: error on macro invocations with missing argument lists
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2021-02-19 09:18:41 -05:00 |
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macro_unapplied_newline.ys
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verilog: error on macro invocations with missing argument lists
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2021-02-19 09:18:41 -05:00 |
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mem_bounds.sv
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mem2reg: tolerate out of bounds constant accesses
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2021-06-08 15:02:57 -04:00 |
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mem_bounds.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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module_end_label.ys
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sv: fix up end label checking
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2021-06-16 21:48:05 -04:00 |
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net_types.sv
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sv: support wand and wor of data types
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2021-09-21 14:52:28 -04:00 |
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net_types.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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package_end_label.ys
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sv: check validity of package end label
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2021-05-10 14:37:32 -04:00 |
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package_task_func.sv
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sv: support tasks and functions within packages
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2021-06-01 13:17:41 -04:00 |
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package_task_func.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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param_int_types.sv
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sv: extended support for integer types
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2021-02-28 16:31:56 -05:00 |
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param_int_types.ys
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sv: extended support for integer types
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2021-02-28 16:31:56 -05:00 |
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param_no_default.sv
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sv: support for parameters without default values
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2021-03-02 10:43:53 -05:00 |
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param_no_default.ys
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hierarchy: Without a known top module, derive all deferred modules
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2024-02-06 10:31:40 +01:00 |
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param_no_default_not_svmode.ys
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sv: support for parameters without default values
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2021-03-02 10:43:53 -05:00 |
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param_no_default_unbound_1.ys
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sv: support for parameters without default values
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2021-03-02 10:43:53 -05:00 |
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param_no_default_unbound_2.ys
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sv: support for parameters without default values
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2021-03-02 10:43:53 -05:00 |
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param_no_default_unbound_3.ys
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sv: support for parameters without default values
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2021-03-02 10:43:53 -05:00 |
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param_no_default_unbound_4.ys
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sv: support for parameters without default values
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2021-03-02 10:43:53 -05:00 |
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param_no_default_unbound_5.ys
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sv: support for parameters without default values
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2021-03-02 10:43:53 -05:00 |
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parameters_across_files.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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past_signedness.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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port_int_types.sv
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verilog: fix sizing of ports with int types in module headers
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2021-03-01 13:39:05 -05:00 |
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port_int_types.ys
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verilog: fix sizing of ports with int types in module headers
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2021-03-01 13:39:05 -05:00 |
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prefix.sv
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verilog: fix multiple AST_PREFIX scope resolution issues
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2021-09-21 12:10:59 -04:00 |
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prefix.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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roundtrip_proc.ys
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Test roundtripping some processes to Verilog and back
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2024-01-24 16:32:25 +00:00 |
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run-test.sh
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test: restore verific handling, nicer naming
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2024-12-13 10:24:47 +01:00 |
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sign_array_query.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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size_cast.sv
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Added cast to type support (#4284)
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2024-09-29 17:03:01 -04:00 |
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size_cast.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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struct_access.sv
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Fix access to whole sub-structs (#3086)
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2022-02-14 14:34:20 +01:00 |
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struct_access.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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task_attr.ys
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sv: support assignments within expressions
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2023-09-05 22:27:55 -04:00 |
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typedef_across_files.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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typedef_const_shadow.sv
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Add test for typenames using constants shadowed later on
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2023-02-12 17:03:37 -05:00 |
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typedef_const_shadow.ys
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Add test for typenames using constants shadowed later on
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2023-02-12 17:03:37 -05:00 |
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typedef_legacy_conflict.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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unbased_unsized.sv
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sv: fix some edge cases for unbased unsized literals
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2021-03-06 15:20:34 -05:00 |
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unbased_unsized.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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unbased_unsized_shift.sv
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verilog: Fix const eval of unbased unsized constants
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2023-04-20 12:12:50 +02:00 |
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unbased_unsized_shift.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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unbased_unsized_tern.sv
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verilog: use derived module info to elaborate cell connections
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2021-10-25 18:25:50 -07:00 |
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unbased_unsized_tern.ys
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verilog: use derived module info to elaborate cell connections
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2021-10-25 18:25:50 -07:00 |
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unmatched_else.ys
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verilog: fix handling of nested ifdef directives
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2021-03-01 12:28:33 -05:00 |
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unmatched_elsif.ys
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verilog: fix handling of nested ifdef directives
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2021-03-01 12:28:33 -05:00 |
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unmatched_endif.ys
|
verilog: fix handling of nested ifdef directives
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2021-03-01 12:28:33 -05:00 |
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unmatched_endif_2.ys
|
preproc: test coverage for #2712
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2021-03-30 12:23:18 -04:00 |
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unnamed_block.ys
|
verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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unnamed_genblk.sv
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verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
|
unnamed_genblk.ys
|
verilog: significant block scoping improvements
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2021-01-31 09:42:09 -05:00 |
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unreachable_case_sign.ys
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tests: Run async2sync before sat and/or sim to handle $check cells
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2024-02-01 16:14:11 +01:00 |
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upto.ys
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techlibs/common: more robustness when *_WIDTH = 0
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2020-05-05 08:01:27 -07:00 |
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void_func.ys
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verilog: Support void functions
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2023-03-20 12:52:46 +01:00 |
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wire_and_var.sv
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sv: fix support wire and var data type modifiers
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2021-01-20 09:16:21 -07:00 |
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wire_and_var.ys
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sv: fix support wire and var data type modifiers
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2021-01-20 09:16:21 -07:00 |
