mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 17:44:09 +00:00
081d9318bc
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
115 lines
2.2 KiB
Plaintext
115 lines
2.2 KiB
Plaintext
bram $__ECP5_PDPW16KD
|
|
init 1
|
|
|
|
abits 9
|
|
dbits 36
|
|
|
|
groups 2
|
|
ports 1 1
|
|
wrmode 1 0
|
|
enable 4 1
|
|
transp 0 0
|
|
clocks 2 3
|
|
clkpol 2 3
|
|
endbram
|
|
|
|
bram $__ECP5_DP16KD
|
|
init 1
|
|
|
|
abits 10 @a10d18
|
|
dbits 18 @a10d18
|
|
abits 11 @a11d9
|
|
dbits 9 @a11d9
|
|
abits 12 @a12d4
|
|
dbits 4 @a12d4
|
|
abits 13 @a13d2
|
|
dbits 2 @a13d2
|
|
abits 14 @a14d1
|
|
dbits 1 @a14d1
|
|
|
|
groups 2
|
|
ports 1 1
|
|
wrmode 1 0
|
|
enable 2 1 @a10d18
|
|
enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1
|
|
transp 0 2
|
|
clocks 2 3
|
|
clkpol 2 3
|
|
endbram
|
|
|
|
# The syn_* attributes are described in:
|
|
# https://www.latticesemi.com/-/media/LatticeSemi/Documents/Tutorials/AK/LatticeDiamondTutorial311.ashx
|
|
attr_icase 1
|
|
|
|
match $__ECP5_PDPW16KD
|
|
# implicitly requested RAM or ROM
|
|
attribute !syn_ramstyle syn_ramstyle=auto
|
|
attribute !syn_romstyle syn_romstyle=auto
|
|
attribute !ram_block
|
|
attribute !rom_block
|
|
attribute !logic_block
|
|
min bits 2048
|
|
min efficiency 5
|
|
shuffle_enable A
|
|
make_transp
|
|
or_next_if_better
|
|
endmatch
|
|
|
|
match $__ECP5_PDPW16KD
|
|
# explicitly requested RAM
|
|
attribute syn_ramstyle=block_ram ram_block
|
|
attribute !syn_romstyle
|
|
attribute !rom_block
|
|
attribute !logic_block
|
|
min wports 1
|
|
shuffle_enable A
|
|
make_transp
|
|
or_next_if_better
|
|
endmatch
|
|
|
|
match $__ECP5_PDPW16KD
|
|
# explicitly requested ROM
|
|
attribute syn_romstyle=ebr rom_block
|
|
attribute !syn_ramstyle
|
|
attribute !ram_block
|
|
attribute !logic_block
|
|
max wports 0
|
|
shuffle_enable A
|
|
make_transp
|
|
or_next_if_better
|
|
endmatch
|
|
|
|
match $__ECP5_DP16KD
|
|
# implicitly requested RAM or ROM
|
|
attribute !syn_ramstyle syn_ramstyle=auto
|
|
attribute !syn_romstyle syn_romstyle=auto
|
|
attribute !ram_block
|
|
attribute !rom_block
|
|
attribute !logic_block
|
|
min bits 2048
|
|
min efficiency 5
|
|
shuffle_enable A
|
|
or_next_if_better
|
|
endmatch
|
|
|
|
match $__ECP5_DP16KD
|
|
# explicitly requested RAM
|
|
attribute syn_ramstyle=block_ram ram_block
|
|
attribute !syn_romstyle
|
|
attribute !rom_block
|
|
attribute !logic_block
|
|
min wports 1
|
|
shuffle_enable A
|
|
or_next_if_better
|
|
endmatch
|
|
|
|
match $__ECP5_DP16KD
|
|
# explicitly requested ROM
|
|
attribute syn_romstyle=ebr rom_block
|
|
attribute !syn_ramstyle
|
|
attribute !ram_block
|
|
attribute !logic_block
|
|
max wports 0
|
|
shuffle_enable A
|
|
endmatch
|