mirror of
https://github.com/YosysHQ/yosys
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081d9318bc
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
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| .. | ||
| tests | ||
| .gitignore | ||
| abc9_5g.box | ||
| abc9_5g.lut | ||
| abc9_5g_nowide.lut | ||
| abc9_map.v | ||
| abc9_model.v | ||
| abc9_unmap.v | ||
| arith_map.v | ||
| brams.txt | ||
| brams_connect.py | ||
| brams_init.py | ||
| brams_map.v | ||
| cells_bb.v | ||
| cells_ff.vh | ||
| cells_io.vh | ||
| cells_map.v | ||
| cells_sim.v | ||
| dsp_map.v | ||
| ecp5_ffinit.cc | ||
| ecp5_gsr.cc | ||
| latches_map.v | ||
| lutrams.txt | ||
| lutrams_map.v | ||
| Makefile.inc | ||
| synth_ecp5.cc | ||