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yosys/tests/liberty/semicolmissing.lib.verilogsim.ok

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module fulladder (A, B, CI, CO, Y);
input A;
input B;
input CI;
output CO;
assign CO = (((A&B)|(B&CI))|(CI&A)); // "(((A * B)+(B * CI))+(CI * A))"
output Y;
assign Y = ((A^B)^CI); // "((A^B)^CI)"
endmodule