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90 lines
2.9 KiB
Text
90 lines
2.9 KiB
Text
design -reset
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read_verilog <<EOT
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module cascade(input clk, input [4:0] a, input [4:0] b, output reg [9:0] o);
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reg [4:0] ar1, ar2, ar3, br1, br2, br3;
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reg [9:0] m, n;
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always @(posedge clk) begin
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ar1 <= a;
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ar2 <= ar1;
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ar3 <= ar2;
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br1 <= b;
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br2 <= br1;
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br3 <= br2;
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m <= ar1 * br1;
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n <= ar2 * br2 + m;
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o <= ar3 * br3 + n;
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end
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endmodule
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EOT
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proc
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design -save read
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
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design -load postopt
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cd cascade
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select -assert-count 3 t:DSP48E1
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select -assert-none t:DSP48E1 t:BUFG %% t:* %D
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# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
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# (i.e. Take all DSP48E1s, expand to find all wires connected
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# to its PCOUT port, then remove all DSP48E1s from this
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# selection, then expand again to find all cells where
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# those wires are connected to the PCIN port, then remove
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# all wires from this selection, and lastly intersect
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# this selection with all DSP48E1 cells (to check that
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# the connected cells are indeed DSPs)
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select -assert-count 2 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i
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design -load read
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
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design -load postopt
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cd cascade
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select -assert-count 3 t:DSP48A1
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select -assert-count 5 t:FDRE # No cascade for A input
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select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
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# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
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# (see above for explanation)
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select -assert-count 2 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i
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design -reset
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read_verilog <<EOT
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module cascade(input clk, input [4:0] a, input [4:0] b, output reg [9:0] o);
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reg [4:0] ar1, ar2, ar3, br1, br2, br3;
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reg [9:0] m;
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always @(posedge clk) begin
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ar1 <= a;
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ar2 <= ar1;
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ar3 <= ar2;
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br1 <= b;
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br2 <= br1;
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br3 <= br2;
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m <= ar2 * br2;
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o <= ar3 * br3 + m;
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end
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endmodule
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EOT
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proc
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design -save read
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
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design -load postopt
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cd cascade
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select -assert-count 2 t:DSP48E1
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# TODO Disabled check, FDREs emitted due to order sensitivity
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# select -assert-none t:DSP48E1 t:BUFG %% t:* %D
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# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
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# (see above for explanation)
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select -assert-count 1 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i
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design -load read
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equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
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design -load postopt
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cd cascade
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select -assert-count 2 t:DSP48A1
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select -assert-count 10 t:FDRE # Cannot cascade because first 'm' DSP
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# uses both B0REG and B1REG, whereas 'o'
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# only requires 1
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select -assert-none t:DSP48A1 t:BUFG t:FDRE %% t:* %D
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# Very crude method of checking that DSP48E1.PCOUT -> DSP48E1.PCIN
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# (see above for explanation)
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select -assert-count 1 t:DSP48A1 %co:+[PCOUT] t:DSP48A1 %d %co:+[PCIN] w:* %d t:DSP48A1 %i
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