Rupert Swarbrick 044ca9dde4 Add support for SystemVerilog-style `define to Verilog frontend ... This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.		2020-03-27 16:08:26 +00:00
..
.gitignore	Add "make coverage"	2018-08-27 14:22:21 +02:00
const2ast.cc	Fix handling of z_digit "?" and fix optimization of cmp with "z"	2019-09-13 13:39:39 +02:00
Makefile.inc	Add one mode dependency	2020-03-19 16:53:40 +01:00
preproc.cc	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
preproc.h	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
verilog_frontend.cc	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
verilog_frontend.h	Add support for SystemVerilog-style `define to Verilog frontend	2020-03-27 16:08:26 +00:00
verilog_lexer.l	Parser changes to support typedef.	2020-03-22 18:20:46 -07:00
verilog_parser.y	Clear pkg_user_types if no packages following a 'design -reset-vlog'.	2020-03-22 18:20:46 -07:00